Our Team

After earning his degree in Computer Engineering at Virginia Tech, David spent several years at Intel in graphics hardware architecture. He is currently a Computer Systems Engineer at Lawrence Berkeley National Labs. His research interests are focused on the design and simulation of future exascale systems with a focus on processor architecture.

Dr. Myoungsoo Jung is Assistant Professor at The University of Texas at Dallas. His research is supported by and in collaboration with the Department of Energy, the National Science Foundation, SK-Hynix semiconductor company (formerly Hyundai Electronics), and the National Energy Research Scientific Computing Center in Oakland, California; the total amount of active projects exceeds $2.2M, and his lab secures more than $1M as a single PI and an UT-Dallas PI. He also works with Lawrence Berkeley National Laboratory as Guest Research Scientist, to model and simulate diverse memory technologies on scientific applications in designing energy-efficient Exascale computing systems. In addition to his academic activities, Dr. Jung has many years of industry experience, several industrial U.S. patents related to multi-channel SSDs, and approximately thirty technical papers regarding SSD flash firmware and kernel-level file systems. Dr. Jung earned his Ph.D. in Computer Science at Pennsylvania State University and his M.S. in Computer Science from Georgia Institute of Technology, and an M.S. in Embedded System from Korea University in Seoul.

John Shalf is Department Head for Computer Science at the LBNL Computing Research Division (CRD) and CTO for the National Energy Research Supercomputing Center (NERSC) Division of Lawrence Berkeley National Laboratory. Prior to that, John led the LBNL’s Advanced Technology Group for nearly a decade. John is a co-author of over 60 publications in the field of software frameworks and HPC technology. He currently leads the DOE Computer Architecture Laboratory.

John is a software engineering enthusiast and a Computing Systems Engineer in the Future Technologies Group at Lawrence Berkeley National Lab. His interests span programming languages (high-level functional and systems level), to software engineering methodologies. At present his research is based in intrumentation-driven simulation of hardware for exascale. This includes cache coherency in memory hierarchies and the performance of asynchronous task-based runtimes. The challenges of building an infrastructure for highly-parameterized hardware components has drawn him into the clutches of this group.

Cy Chan is a computational science post-doctoral research fellow in FTG working on developing new techniques for software optimization and novel programming models for HPC systems. His current research interests include the analysis and optimization of multi-resolution, multi-physics, fluid-simulation codes for hardware/software co-design and the development of new programming models and runtime systems to automate this process for future exascale systems. His recent work has also introduced and studied auto-tuners for solving sparse linear systems including multigrid solvers. In addition to these pursuits, he is also interested in developing collaborations in other areas of renewable energy applications research. He holds an A.B. in Applied Mathematics from Harvard University and an S.M. and Ph.D. in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology.

Farzad is an FPGA Computing Systems Engineer in the Future Technologies Group at Lawrence Berkeley National Labs. He graduated from the University of California, Berkeley with a degree in Electrical Engineering and Computer Science. He spent several years designing FPGA platforms used in HPC applications for a startup company prior to coming the Lab. His research interests are focused on embedded and mobile systems in the HPC design space.

George is a postdoctoral research fellow at LBNL and is a member of the CAL group. His past work focuses on on-chip network with numerous contributions to flow control, congestion, allocation, and co-design with chip multiprocessors. His other work includes congestion control for system-wide networks, precision loss avoidance for system-wide reduction operations, and maximizing DRAM and on-chip data movement efficiency by taking advantage of advanced language constructs.

He does stuff.